A design strategy for a 1-V rail-to-rail input/output CMOS opamp

Author

Fayomi, Christian Jesus B ; Sawan, Moharnad ; Roberts, Gordon W.

Author_Institution

Dept. of Electr. & Comput. Eng., Ecole Polytech. de Montreal, Que., Canada

Volume

1

fYear

2001

fDate

6-9 May 2001

Firstpage

639

Abstract

A design strategy for a rail-to-rail input/output operational amplifier in standard CMOS 0.18 μm digital process with a 0.5-V threshold is presented. It uses a novel level shifting technique of the input signal and a dynamically biased class AB output stage based on a switched-capacitor configuration. The amplifier is capable of working with a power supply as low as 1-V while providing a 26.6 MHz unity gain frequency and a 67 degree phase margin with a load condition of 5 pF and 20 kΩ. The overall circuit dissipates 400 μW

Keywords

CMOS analogue integrated circuits; SPICE; frequency response; integrated circuit design; low-power electronics; operational amplifiers; switched capacitor networks; 1 V; 20 kohm; 5 pF; HSPICE; LV design; design strategy; differential input pair; dynamically biased class AB output stage; frequency response; level shifting technique; rail-to-rail input/output CMOS op amp; switched-capacitor configuration; CMOS process; Circuits; Dynamic range; Laboratories; Microelectronics; Operational amplifiers; Power supplies; Rail to rail inputs; Voltage; Wide area networks;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on

Conference_Location

Sydney, NSW

Print_ISBN

0-7803-6685-9

Type

conf

DOI

10.1109/ISCAS.2001.921937

Filename

921937