Three stage low noise operational amplifier design for a 0.18 um CMOS process

Author

Soltani, Ali ; Yaghmaie, M. ; Razeghi, Behrooz ; Pourandoost, R. ; Tous, S.I. ; Golmakani, Abbas

Author_Institution

Dept. of Electr. Eng., Sadjad Inst. of Higher Educ., Mashhad, Iran

fYear

2012

fDate

26-28 Sept. 2012

Firstpage

1

Lastpage

4

Abstract

A new three stage low-noise, high-gain operational amplifier (Op-Amp) is proposed in this paper. Design strategies are discussed for minimizing noise and increasing gain. Multipath nested Miller compensation used for three stage operational amplifier. The circuit is designed in the 0.18μm CMOS technology. The HSPICE software was used for simulation. The simulation results show that the amplifier has a 128.5 dB open-loop DC gain and a unity gain-bandwidth of 794 MHz. Also input-referred noise of this circuit is 1.233 (nF/√(Hz)) at 1 MHz frequency.

Keywords

CMOS analogue integrated circuits; SPICE; low noise amplifiers; operational amplifiers; thermal noise; CMOS process; HSPICE software; bandwidth 794 MHz; frequency 1 MHz; gain 128.5 dB; high-gain operational amplifier; input-referred noise; low noise operational amplifier; multipath nested Miller compensation; op-amp; open-loop DC gain; size 0.18 micron; unity gain-bandwidth; 1f noise; CMOS integrated circuits; Gain; Logic gates; Operational amplifiers; Thermal noise; Flicker noise; Nested Miller compensation; Noise; Thermal noise; three stage operational Amplifier;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Engineering, Computing Science and Automatic Control (CCE), 2012 9th International Conference on

Conference_Location

Mexico City

Print_ISBN

978-1-4673-2170-9

Type

conf

DOI

10.1109/ICEEE.2012.6421117

Filename

6421117