Title :
Planarization of dual-damascene post-metal-CMP structures
Author :
Lin, Chenting ; Clevenger, Larry ; Schnabel, Florian ; Jamin, Fen Fen ; Dobuzinski, David
Author_Institution :
DRAM Dev. Alliance, Siemens Microelectron. Inc., Hopewell Junction, NY, USA
Abstract :
Metal CMP of dual damascene structures can result in localized topography being introduced into a chip by metal dishing and oxide erosion. The higher the local metal pattern factor, the larger the amount of topography introduced during CMP. This work investigates methods to reduce this additional topography. In our approach, a deeper damascene trench than required is etched and then filled with metal. Then, immediately following metal CMP, the metal CMP slurry flow is stopped and a slurry targeted for oxide removal is introduced to planarize the areas with high metal pattern factors. This planarization CMP procedure reduces the surface topography created during metal CMP and introduces additional metal loss. The additional metal loss is compensated by the deeper damascene trenches. Using this approach, step height and electrical analysis confirm large reductions in topography without an increase in the targeted sheet resistance
Keywords :
abrasion; chemical mechanical polishing; etching; integrated circuit interconnections; integrated circuit metallisation; integrated circuit testing; surface chemistry; surface topography; damascene trench depth; damascene trenches; dual damascene structures; dual-damascene post-metal-CMP structures; electrical analysis; etching; local metal pattern factor; localized topography; metal CMP; metal CMP slurry flow; metal dishing; metal filling; metal loss; metal pattern factors; oxide erosion; oxide removal slurry; planarization; planarization CMP procedure; step height; surface topography; targeted sheet resistance; Dielectrics; Electric resistance; Etching; Lithography; Microelectronics; Planarization; Random access memory; Slurries; Surface resistance; Surface topography;
Conference_Titel :
Interconnect Technology, 1999. IEEE International Conference
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-5174-6
DOI :
10.1109/IITC.1999.787086