DocumentCode :
3084956
Title :
A global postsynthesis optimization method for combinational circuits
Author :
Vasicek, Zdenek ; Sekanina, Lukas
Author_Institution :
Fac. of Inf. Technol., Brno Univ. of Technol., Brno, Czech Republic
fYear :
2011
fDate :
14-18 March 2011
Firstpage :
1
Lastpage :
4
Abstract :
A genetic programming-based circuit synthesis method is proposed that enables to globally optimize the number of gates in circuits that have already been synthesized using common methods such as ABC and SIS. The main contribution is a proposal for a new fitness function that enables to significantly reduce the fitness evaluation time in comparison to the state of the art. The fitness function performs optimized equivalence checking using a SAT solver. It is shown that the equivalence checking time can significantly be reduced when knowledge of the parent circuit and its mutated offspring is taken into account. For a cost of a runtime, results of conventional synthesis conducted using SIS and ABC were improved by 20-40% for the LGSynth93 benchmarks.
Keywords :
circuit optimisation; combinational circuits; computability; equivalent circuits; genetic algorithms; logic design; logic gates; SAT solver; circuit gates; combinational circuit; equivalence checking time; fitness evaluation time; fitness function; genetic programming-based circuit synthesis; global postsynthesis optimization; mutated offspring; parent circuit; Analog circuits; Benchmark testing; Circuit synthesis; Genetic programming; Indexes; Logic gates; Runtime;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011
Conference_Location :
Grenoble
ISSN :
1530-1591
Print_ISBN :
978-1-61284-208-0
Type :
conf
DOI :
10.1109/DATE.2011.5763326
Filename :
5763326
Link To Document :
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