DocumentCode :
3084962
Title :
Highly linear 100 MHz CMOS programmable gain amplifiers
Author :
Hsu, Cheng Chung ; Wu, Jieh Tsorng
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Volume :
1
fYear :
2001
fDate :
6-9 May 2001
Firstpage :
647
Abstract :
Digitally programmable gain amplifiers (PGAs) are designed by using the current-mode technique to achieve constant bandwidth and high linearity. A new current amplifier and MOS switch arrays are proposed to realize the PGAs. Simulation results show that, implemented in a standard 0.35 μm CMOS technology, the amplifier exhibits a total harmonic distortion of lower than -60 dB for an 80 MHz differential output with 1.6 V peak-to-peak voltage. Dissipating 22 mW from a 3.3 V supply, a single-stage PGA can have a voltage gain varying from 0 dB to 20 dB while maintaining a constant bandwidth of 100 MHz driving 2 pF capacitive loads
Keywords :
CMOS analogue integrated circuits; current-mode circuits; feedback amplifiers; harmonic distortion; operational amplifiers; programmable circuits; 0 to 20 dB; 100 MHz; 2 pF; 3.3 V; CMOS programmable gain amplifiers; MOS switch arrays; capacitive load; closed-loop feedback; constant bandwidth; current amplifier; current-mode technique; differential output; high linearity; low total harmonic distortion; two-stage amplifier; Bandwidth; Circuits; Electronics packaging; Feedback; Linearity; Operational amplifiers; Power dissipation; Resistors; Transconductance; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location :
Sydney, NSW
Print_ISBN :
0-7803-6685-9
Type :
conf
DOI :
10.1109/ISCAS.2001.921939
Filename :
921939
Link To Document :
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