The nanoelectronic CMOS era: silicon meets the other materials on the roadmap

Historically, innovations have been possible because of the strong association of devices and materials research. The demand for low voltage, low power and high performance are the great challenges for engineering of sub 50 nm gate length CMOS devices. We point out the main issues to address in order to investigate and push the limits of CMOS technology. The alternative architectures allowing to increase devices drivability and reduce power are reviewed. Among the materials options to be integrated, HiK gate dielectric and metal gate are among the most strategic options to consider for power consumption and low supply voltage management. New architectures and options are reviewed through the issues to address in gate/channel and substrate, gate dielectric as well as source and drain engineering. It will be very difficult to compete with CMOS logic because of the low series resistance required to obtain high performance. By introducing new materials, Si based CMOS will be scaled beyond the ITRS as the future System-on-Chip Platform integrating new disruptive devices. Functionality of devices in the range of 5 nm channel length has been demonstrated showing that CMOS technology could still be used in the future if we manage to implement new materials and device architecture options.