Overview of the prospects of ultra-rapid thermal process for advanced CMOSFETs

Author

Suguro, Kyoichi ; Ito, Takayuki ; Matsuo, Kouji ; Iinuma, T. ; Nishinohara, Kazumi T.

Author_Institution

Process & Manuf. Eng. Center, Toshiba Corp., Yokohama, Japan

fYear

2004

fDate

15-16 March 2004

Firstpage

18

Lastpage

21

Abstract

This paper presents ultra shallow junction with low resistance in 45-65nm technology node. Rapid thermal annealing is required to form ultra-shallow, low sheet resistance and lower dislocation density for satisfying the pn junction leakage specification of mobile LSIs. In order to minimize the annealing time at high temperatures, various kinds of ultra-rapid thermal annealing technology such as advanced spike RTA, laser annealing, SPE, flash lamp annealing are compared. Issues of this technology are simultaneously accomplishing ultrashallow Xj, lower sheet resistance and lower crystal damage density for fabricating advanced MOSFETs. By optimizing various process conditions, we can successfully obtain ultra shallow p+/n and n+/p junction of less than 10 nm. In this paper, we overview the prospects for ultra-rapid thermal process for advanced CMOSFETs.

Keywords

CMOS integrated circuits; MOSFET; nanotechnology; rapid thermal annealing; 10 nm; 45 to 65 nm; 45-65nm technology node; SPE; advanced CMOSFETs; flash lamp annealing; laser annealing; low resistance; lower crystal damage density; lower sheet resistance; pn junction leakage specification; rapid thermal annealing; spike RTA; ultra shallow junction; ultra-rapid thermal process; CMOSFETs; Conductivity; Impurities; Lamps; MOSFETs; Plasma temperature; Rapid thermal annealing; Rapid thermal processing; Temperature distribution; Thermal resistance;

fLanguage

English

Publisher

ieee

Conference_Titel

Junction Technology, 2004. IWJT '04. The Fourth International Workshop on

Print_ISBN

0-7803-8191-2

Type

conf

DOI

10.1109/IWJT.2004.1306748

Filename

1306748