Photolithography solutions for fabrication of Fin and Poly-gate in 14nm FinFET devices

Due to good electrical characteristics and controllability, 3D-FinFET is proved to be a promising substitution of planar poly-gate devices for 20nm technology node and beyond. One of the greatest challenges is to fabricate the Fin and Poly-gate to meet device requirement. This paper describes the photolithography process as one of key solutions to form Fin and Poly-gate structure in 14nm FinFET devices. To fabricate the Fin structure, SADP (Self Aligned Double Patterning) process is introduced to obtain 25nm half pitch pattern; furthermore, the overlay performance, which is impacted by SADP process, is studied on both design of alignment/overlay mark and light source of overlay measurement. Lithography performance of LELE (Lihto-Etch-Litho-Etch) double-patterning is described in poly line formation. LEC (Line End Cutting) process with various groups of materials is discussed to improve poly line-end performance. Finally, a desired FinFET structure is successfully fabricated.