Title :
Influence of sidewall roughness on the reliability of 0.20-μm Al RIE wiring
Author :
Ravikumar, R. ; Cichy, H. ; Filippi, R.G. ; Kiewra, E.W. ; Rath, D.L. ; Stojakovic, G.
Author_Institution :
DRAM Dev. Alliance, Siemens Microelectron. Inc., Hopewell Junction, NY, USA
Abstract :
Aluminum based wiring is widely used in the back-end-of-line (BEOL) metallization of integrated circuits. In a 256 Mb dynamic random access memory (DRAM) product, the first level of Al wiring exists at a 0.20 μm ground rule. Performance and reliability issues from these aggressive ground rules result in serious challenges for semiconductor fabrication processing at the BEOL. This paper compares two different sidewall roughness profiles which were created by varying the post-metal etch wet clean. The resulting “rough” and “smooth” sidewall profiles are correlated with the electrical performance and reliability characteristics of the 256 Mb-DRAM product
Keywords :
DRAM chips; aluminium; integrated circuit interconnections; integrated circuit metallisation; integrated circuit reliability; integrated circuit testing; sputter etching; surface cleaning; surface topography; 0.2 micron; 256 Mbit; Al; Al RIE wiring; Al wiring; BEOL metallization; DRAM; DRAM product; aluminum based wiring; back-end-of-line metallization; dynamic random access memory product; electrical performance; ground rule; integrated circuits; post-metal etch wet clean; reliability; reliability characteristics; rough sidewall profile; semiconductor fabrication processing; sidewall roughness; sidewall roughness profiles; smooth sidewall profile; Aluminum; Copper; Current density; Electric resistance; Electromigration; Microelectronics; Random access memory; Testing; Wet etching; Wiring;
Conference_Titel :
Interconnect Technology, 1999. IEEE International Conference
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-5174-6
DOI :
10.1109/IITC.1999.787104
