DocumentCode :
3085287
Title :
On practical stable packet scheduling for bufferless three-stage Clos-network switches
Author :
Yu Xia ; Chao, H. Jonathan
Author_Institution :
Dept. of Comput. Sci. & Eng., Hong Kong Univ. of Sci. & Technol., Hong Kong, China
fYear :
2013
fDate :
8-11 July 2013
Firstpage :
7
Lastpage :
14
Abstract :
In this paper, we extend our previous work of StablePlus, a stable scheduling algorithm for single-stage packet switches, to bufferless three-stage Clos-network switches. StablePlus is based on an existing stable distributed scheduling algorithm, called DISQUO. We further improve the switching performance by incorporating a heuristic scheduling algorithm after the DISQUO scheduling. In a three-stage Clos-network switch, DISQUO is first used to solve the output contention which generates a stable matching between the input and output ports, then Karol´s algorithm is used to find the feasible internal paths for the matched input and output pairs. However, the latter requires multiple mini-cycles to complete the path-finding task. Worse is that the number of mini-cycles increases as the switch size does, limiting the Clos-network to a small implementable size. By replacing the Hamiltonian Walk in DISQUO with time-division multiplexing (TDM) scheme, we show that the number of required mini-cycles for Karol´s algorithm can be reduced to only two, independent of the switch size. Moreover, with the help of a parallel hardware approach, we can implement packet scheduling in O(1) time complexity. To support high data rates, e.g., 100 Gbps, we can also make the scheduling work on a frame basis. We prove that StablePlus can achieve 100% throughput under any admissible traffic, and by simulations we show that it also has good delay performance.
Keywords :
packet switching; scheduling; telecommunication traffic; time division multiplexing; DISQUO scheduling; Hamiltonian walk; Karols algorithm; StablePlus; TDM scheme; bufferless three-stage Clos-network switches; clos network switches; distributed scheduling algorithm; heuristic scheduling algorithm; path finding task; practical stable packet scheduling; single stage packet switches; time division multiplexing; Availability; Delays; Indexes; Ports (Computers); Scheduling algorithms; Throughput; Time division multiplexing; 100% throughput; Hybrid Algorithm; StablePlus; Strictly Non-Blocking; Three-stage Clos-Network Switch;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
High Performance Switching and Routing (HPSR), 2013 IEEE 14th International Conference on
Conference_Location :
Taipei
ISSN :
2325-5552
Type :
conf
DOI :
10.1109/HPSR.2013.6602283
Filename :
6602283
Link To Document :
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