Heterogeneous 3D integration — Technology enabler toward future super-chip

To overcome various concerns caused by scaling-down the device size, it is indispensable to introduce a new concept of heterogeneous 3D integration called a super-chip in which various kinds of device chips with different size, different devices and different materials are stacked. A key technology of self-assembly and electrostatic (SAE) temporary bonding has been developed to achieve a super-chip. Several kinds of super-chips are fabricated by stacking compound semiconductor device chip, photonic device chip and spintronic device chip on CMOS device chips.