DocumentCode :
3085438
Title :
Introduction of system level architecture exploration using the SpecC methodology
Author :
Cai, L. ; Gajski, D. ; Olivarez, M.
Author_Institution :
Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
Volume :
5
fYear :
2001
fDate :
2001
Firstpage :
9
Abstract :
To implement chip design on satisfactory target architectures, architecture exploration should be done at higher levels of abstraction, in the earliest design stages. Using the SpecC language, an executable system level design language, system level architecture exploration can proceed easily and smoothly as the system specification is being created. A SpecC methodology of system level architecture exploration is introduced within this paper to illustrate this process. The design of a JPEG encoder is used as an example to illustrate the system level architecture exploration methodology
Keywords :
application specific integrated circuits; circuit CAD; circuit simulation; high level synthesis; integrated circuit design; JPEG encoder; SpecC language; SpecC methodology; chip design; executable system level design language; system level architecture exploration; Chip scale packaging; Computer architecture; Computer science; Design methodology; Process design; Specification languages; System testing; System-level design; Time to market; Transform coding;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location :
Sydney, NSW
Print_ISBN :
0-7803-6685-9
Type :
conf
DOI :
10.1109/ISCAS.2001.921971
Filename :
921971
Link To Document :
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