Title :
Process integration of double level copper-low k (k=2.8) interconnect
Author :
Naik, M. ; Parikh, S. ; Li, P. ; Educato, J. ; Cheung, D. ; Hashim, I. ; Hey, P. ; Jenq, S. ; Pan, T. ; Redeker, F. ; Rana, V. ; Tang, B. ; Yost, D.
Author_Institution :
Appl. Mater. Inc., Santa Clara, CA, USA
Abstract :
This paper reports a comparative study of double level copper interconnects using Black Diamond (k=2.8) dielectric, fluorinated silicate glass (FSG, k=3.7) and undoped silicate glass (USG, k=4.1). A 25-28% reduction in intra-lead capacitance is realized with k=2.8 dielectric compared to USG. Intra-lead electrical isolation, single via and via chain resistances are comparable for the dielectrics. The linearity of electrically measured line widths and serpent resistances indicate that Black Diamond CMP performance is comparable to USG and FSG. Preliminary wafer level electromigration data for the copper/low-k dielectric is comparable to copper/USG
Keywords :
capacitance; chemical mechanical polishing; copper; dielectric thin films; electric resistance; electromigration; glass; integrated circuit interconnections; integrated circuit metallisation; integrated circuit reliability; Black Diamond CMP performance; Black Diamond dielectric; Cu; FSG; USG; copper/USG; copper/low-k dielectric; dielectrics; double level copper interconnects; double level copper-low k interconnect; electrically measured line width linearity; electrically measured serpent resistance linearity; fluorinated silicate glass; intra-lead capacitance; intra-lead electrical isolation; process integration; single via resistance; undoped silicate glass; via chain resistance; wafer level electromigration; Ash; Capacitance; Copper; Dielectric films; Dielectric materials; Dielectric thin films; Electromigration; Glass; Metallization; Wet etching;
Conference_Titel :
Interconnect Technology, 1999. IEEE International Conference
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-5174-6
DOI :
10.1109/IITC.1999.787115
