DocumentCode
3085590
Title
On tri-state buffer inference in HDL synthesis
Author
Lin, Hen-Ming ; Jou, Jing-Yang
Author_Institution
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Volume
5
fYear
2001
fDate
2001
Firstpage
45
Abstract
Typical synthesizers adopt ad hoc methods to solve the tri-state buffer inference in HDL synthesis. It results in that typical synthesizers may generate wrong netlist whose behaviors are not consistent with that of input HDL description. This paper proposes a systematical method to conduct the tri-state buffer inference correctly. The result comparisons show that our approach can infer the tri-state buffers correctly and does not suffer from the mismatches between synthesis
Keywords
buffer circuits; hardware description languages; high level synthesis; HDL synthesis; HLS; RTL synthesis; netlist; tri-state buffer inference; Circuit synthesis; Flip-flops; Hardware design languages; Impedance; Inference algorithms; Latches; Network synthesis; Registers; Robustness; Synthesizers;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location
Sydney, NSW
Print_ISBN
0-7803-6685-9
Type
conf
DOI
10.1109/ISCAS.2001.921980
Filename
921980
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