Title :
Cleans for Al vias in a 0.175 μm dual damascene process
Author :
Gambino, J. ; Clevenger, L. ; Costrini, G. ; Schnabel, F. ; Ravikumar, R. ; Dobuzinsky, D. ; Iggulden, R. ; Dziobkowski, C. ; Wildman, H. ; Benedict, J. ; Bruley, J. ; Domenicucci, A.
Author_Institution :
IBM Microelectron., IBM Semicond. Res. & Dev. Center, Hopewell Junction, NY, USA
Abstract :
The effect of cleaning processes on via resistance and via continuity has been studied for 0.175 μm Al dual damascene structures used for 1 Gbit DRAMs. Three types of vias have been investigated; high aspect ratio (4:1) Al vias landing on either W or Al damascene interconnects, and relatively low aspect ratio (1.3:1) Al vias landing on Al damascene interconnects. The via resistance depends on both the type of contact and the type of clean. Low via resistance is more difficult to achieve when landing on Al compared to landing on W, due to the low volatility of Al fluorides and due to the high thermal stability of Al oxides
Keywords :
DRAM chips; aluminium; electric resistance; integrated circuit interconnections; integrated circuit metallisation; integrated circuit reliability; surface cleaning; 0.175 micron; 1 Gbit; Al; Al damascene interconnects; Al dual damascene structures; Al fluoride volatility; Al oxide thermal stability; Al via cleaning; Al vias; Al-W; Al2O3; AlF; DRAMs; W damascene interconnects; cleaning processes; dual damascene process; high aspect ratio Al vias; low aspect ratio Al vias; via continuity; via resistance; Contact resistance; Electrical resistance measurement; LAN interconnection; Microelectronics; Pollution measurement; Sputter etching; Thermal resistance; Thermal stability; Tin; Wet etching;
Conference_Titel :
Interconnect Technology, 1999. IEEE International Conference
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-5174-6
DOI :
10.1109/IITC.1999.787123
