PVD aluminum dual damascene interconnection: yield comparison between counterbore and self aligned approaches

Author

Blosse, A. ; Raghuram, U. ; Thekdi, S. ; Koutny, B. ; Lau, G. ; Koh, S.L. ; Goodenough, C. ; Pouëdras, T. ; Sethuraman, A. ; Geha, S. ; Chowdhury, T. ; Guggilla, S. ; Krishna, N. ; Su, J. ; Cha, C. ; Yao, G. ; Price, J.B.

Author_Institution

Cypress Semicond., San Jose, CA, USA

fYear

1999

fDate

1999

Firstpage

215

Lastpage

217

Abstract

A comparative study of the counterbore dual damascene (CBDD) and self-aligned dual damascene (SADD) approaches with aluminum interconnects was carried out for application to 0.18 μm ULSI multilevel interconnects. It is shown that the defect density is lower with the SADD approach. Yield degradation with the CBDD approach is explained by photoresist residues in the bottom of vias, which are difficult to remove due to the high aspect ratio of the holes. The Al-CMP process was optimized by introducing dummy structures to reduce Al dishing on wide interconnect lines. Equivalent yield was demonstrated with the SADD approach in comparison with the standard subtractive aluminum etch process on 0.25 μm SRAM technology

Keywords

SRAM chips; ULSI; aluminium; chemical mechanical polishing; etching; integrated circuit interconnections; integrated circuit metallisation; integrated circuit yield; photoresists; sputter deposition; surface contamination; 0.18 micron; 0.25 micron; Al; Al dishing; Al-CMP process optimization; PVD aluminum dual damascene interconnection; SRAM technology; ULSI multilevel interconnects; aluminum interconnects; counterbore dual damascene; defect density; dummy structures; interconnect yield; photoresist residues; self-aligned dual damascene; subtractive aluminum etch process; via hole aspect ratio; vias; wide interconnect lines; yield degradation; Aluminum; Atherosclerosis; Costs; Etching; Filling; Manufacturing; Random access memory; Resists; Tin; Ultra large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology, 1999. IEEE International Conference

Conference_Location

San Francisco, CA

Print_ISBN

0-7803-5174-6

Type

conf

DOI

10.1109/IITC.1999.787126

Filename

787126