DocumentCode
3085732
Title
Channel-stacked NAND flash memory with layer selection by multi-level operation (LSM)
Author
Wandong Kim ; Joo Yun Seo ; Yoon Kim ; Se Hwan Park ; Sang Ho Lee ; Myung Hyun Baek ; Jong-Ho Lee ; Byung-Gook Park
Author_Institution
Dept. of Electr. Eng., Inter-Univ. Semicond. Res. Center (ISRC), Seoul, South Korea
fYear
2013
fDate
9-11 Dec. 2013
Abstract
In this paper, the channel stacked array (CSTAR) NAND flash memory with layer selection by multi-level operation (LSM) of string select transistor (SST) is proposed and investigated to solve problems of conventional channel stacked array. In case of LSM architecture, the stacked layers can be distinguished by combinations of multi-level states of SST and string select line (SSL) bias. Due to the layer selection performed by the bias of SSL, the placement of bit lines and word lines is similar to the conventional planar structure, and proposed CSTAR with LSM has no island-type SSLs. As a result of the advantages of the proposed architecture, various issues of conventional channel stacked NAND flash memory array can be solved.
Keywords
NAND circuits; flash memories; CSTAR; LSM architecture; SST; bit lines; channel stacked NAND flash memory array; island-type SSL; layer selection; multilevel operation; planar structure; string select line bias; string select transistor; word lines; Arrays; Flash memories; Logic gates; Microprocessors; Silicon; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting (IEDM), 2013 IEEE International
Conference_Location
Washington, DC
Type
conf
DOI
10.1109/IEDM.2013.6724556
Filename
6724556
Link To Document