Circuit impact and skew-corner analysis of stochastic process variation in global interconnect

This paper details the impact of the stochastic interconnect process variation on the circuit performance of global interconnects in deep-submicron logic chips. Signal delay, rise time, and crosstalk variations of global interconnect circuits were first calculated by Monte Carlo simulations using a finite-difference field solver and a SPICE circuit simulator. These circuit performance matrices were subsequently expressed as a response surface function (RSF) of line width, line thickness, and dielectric thickness. The circuit impact was then gauged by a product of sensitivity obtained from the RSF and standard deviation derived from the manufacturing line. Furthermore, the RSF and the joint probability function (JPF) were combined to efficiently generate statistics-based 3-σ process corners. These process corners significantly improved circuit performance bounds in chip design, as compared to the overly pessimistic, conventional worst-case skew-corners