Title :
ST: PERL package for simulation and test environment
Author :
Kobayashi, Kazutoshi ; Onodera, Hidetoshi
Author_Institution :
Graduate Sch. of Inf., Kyoto Univ., Japan
Abstract :
We propose a simulation and test environment called Perl package for Simulation and Test (ST). ST provides an environment to describe unified testbenches for various simulation levels. ST also supports LSI testers. ST is implemented as a Perl package. You can write your testbench according to the Perl syntax. ST supports simulators such as Verilog or SPICE. Expected vectors can be compared with simulated results during Verilog simulation. Bi-directional ports can be handled on SPICE
Keywords :
Perl; SPICE; circuit simulation; hardware description languages; high level synthesis; large scale integration; logic simulation; Perl package; Perl syntax; SPICE; ST; Verilog simulation; bi-directional ports; expected vectors; simulation environment; simulation levels; test environment; unified testbenches; Algorithms; Bidirectional control; Circuit simulation; Circuit testing; Clocks; Hardware design languages; Large scale integration; Packaging; SPICE; Timing;
Conference_Titel :
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location :
Sydney, NSW
Print_ISBN :
0-7803-6685-9
DOI :
10.1109/ISCAS.2001.921992
