A new complementary hetero-junction vertical Tunnel-FET integration scheme

Author

Rooyackers, R. ; Vandooren, A. ; Verhulst, Anne S. ; Walke, A. ; Devriendt, Katia ; Locorotondo, S. ; Demand, Marc ; Bryce, George ; Loo, Roger ; Hikavyy, Andriy ; Vandeweyer, Tom ; Huyghebaert, Cedric ; Collaert, Nadine ; Thean, A.

Author_Institution

Imec, Leuven, Belgium

fYear

2013

fDate

9-11 Dec. 2013

Abstract

This paper presents a new integration scheme for complementary hetero-junction vertical Tunnel FETs (VTFETs), whereby a sacrificial source layer is used during the device fabrication and replaced by the final hetero-source materials, respectively for n- or p-TFETs, thereby minimizing the thermal budget applied to the source junctions. With the demonstration of this source-replacement-last module for a vertical Ge hetero-junction n-TFET, we show that it is possible to grow highly doped hetero-junctions on a Si channel with steep doping profiles and without damaging the high-κ gate-dielectric interface. This scheme allows for the integration of complementary low-bandgap materials on a Si platform providing high on-currents combined with the Si channel based low off-currents.

Keywords

doping profiles; elemental semiconductors; field effect transistors; high-k dielectric thin films; silicon; tunnel transistors; Si; Si channel; Si platform; VTFET; complementary heterojunction; complementary low-bandgap materials; doped heterojunctions; doping profiles; high-κ gate-dielectric interface; n-TFET; p-TFET; source junctions; source layer; source replacement last module; thermal budget; vertical Ge heterojunction; vertical tunnel-FET integration scheme; Dielectrics; Implants; Junctions; Logic gates; Performance evaluation; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting (IEDM), 2013 IEEE International

Conference_Location

Washington, DC

Type

conf

DOI

10.1109/IEDM.2013.6724558

Filename

6724558