Demonstration of improved transient response of inverters with steep slope strained Si NW TFETs by reduction of TAT with pulsed I-V and NW scaling

Author

Knoll, Lars ; Zhao, Q.T. ; Nichau, A. ; Richter, Simon ; Luong, Gia Vinh ; Trellenkamp, Stefan ; Schafer, Andreas ; Selmi, Luca ; Bourdelle, Konstantin K. ; Mantl, Siegfried

Author_Institution

Peter Grunberg Inst. 9, Forschungszentrum Julich, Jülich, Germany

fYear

2013

fDate

9-11 Dec. 2013

Abstract

We present gate all around strained Si (sSi) nanowire array TFETs with high I_ON (64μA/μm at V_DD=1.0V). Pulsed I-V measurements provide small SS and record I₆₀ of 1×10^-2μA/μm at 300K due to the suppression of trap assisted tunneling (TAT). Scaling the nanowires to 10 nm diameter greatly suppresses the impact of TAT and improves SS and I_ON. Transient analysis of complementary TFET inverters demonstrates experimentally for the first time that device scaling and improved electrostatics yields to faster time response.

Keywords

field effect logic circuits; logic gates; nanowires; silicon; thin film transistors; transient analysis; tunnelling; Si; TAT reduction; TFET; gate all around strained nanowire array; inverter transient response; size 10 nm; steep slope strained nanowire; trap assisted tunneling; Electrostatics; Inverters; Junctions; Logic gates; Pulse measurements; Silicon; Tunneling;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting (IEDM), 2013 IEEE International

Conference_Location

Washington, DC

Type

conf

DOI

10.1109/IEDM.2013.6724560

Filename

6724560