Comprehensive layout and process optimization study of Si and III-V technology for sub-7nm node

In this work we present III-V device performance and its variability under various design and process parameters, as compared to Si devices, using MC simulation. III-V device compact/BSIM models are developed, including geometry-dependent parasitic RC. Compared to its Si counterpart, III-V devices exhibit superior performance in I_on, ring oscillator delay (t_pd) and SRAM read time (t_read). We calculated the N_it target for mitigating increments of I_off and subthreshold slopes. For both Si and III-V sub-7nm technology optimization, we propose a direction for technology design to improve performance and area scaling without variability penalty.