Author :
Donaton, R.A. ; Coenagrachts, B. ; Maex, K. ; Struyf, H. ; Vanhaelemeersch, S. ; Beyer, G. ; Richard, E. ; Vervoort, I. ; Fyen, W. ; Grillaert, J. ; Van der Groen, S. ; Stucchi, M. ; De Roest, D.
Abstract :
Single and dual damascene Cu/low k processes are evaluated. Critical integration issues are discussed. Good Cu continuity is obtained over long meanders. The via resistance in dual damascene structures is optimized and the values obtained are almost three times lower than those achieved for a conventional Al/W metallization process. The interline capacitance was evaluated for various etch and strip procedures. The effect of the Cu/low k process on a front end of line 0.25 μm n-MOS process is investigated. The metallization process does not affect the performance of either transistors or field transistors
Keywords :
MOS integrated circuits; capacitance; copper; dielectric thin films; integrated circuit interconnections; integrated circuit metallisation; integrated circuit testing; permittivity; 0.25 micron; Al-W; Al/W metallization process; Cu; Cu continuity; Cu/low k process; copper/low-k dielectric integration; dual damascene Cu/low k processes; dual damascene structures; etch-and-strip procedures; field transistors; front end of line n-MOS process; interline capacitance; metallization process; single damascene Cu/low k processes; transistor performance; via resistance; Artificial intelligence; Atherosclerosis; Chemistry; Copper; Dielectric constant; Dielectric materials; Etching; Metallization; Parasitic capacitance; Polymers;
