Title :
ENISLE: an intuitive heuristic nearly optimal solution for mincut and ratio mincut partitioning
Author :
Cheng, Shun- Wen ; Cheng, Kuo-Hsing
Author_Institution :
Dept. of Electr. Eng., Tamkang Univ., Tamsui, Taiwan
Abstract :
Mincut partitioning is to minimize the total cuts of the edges by the partitioning of nodes into two sets. The proposed method, Edge-Node Interleaved Sort for Leaching and Envelop (ENISLE) algorithm, not only uses node information but also uses edge information. It is simple, but works effectively, and has never appeared in any earlier literature. It can soon obtain an intuitive heuristic nearly optimal solution for mincut and ratio mincut partitioning and, at the same time, is very suitable for EDA usage
Keywords :
VLSI; application specific integrated circuits; circuit layout CAD; field programmable gate arrays; integrated circuit interconnections; integrated circuit layout; iterative methods; logic CAD; logic partitioning; network topology; ENISLE; edge-node interleaved sort for leaching and envelop; edges; intuitive heuristic nearly optimal solution; mincut partitioning; ratio mincut partitioning; Circuit simulation; Circuit testing; Design automation; Electronic design automation and methodology; Integrated circuit interconnections; Iterative methods; Leaching; Partitioning algorithms; System-on-a-chip; Very large scale integration;
Conference_Titel :
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location :
Sydney, NSW
Print_ISBN :
0-7803-6685-9
DOI :
10.1109/ISCAS.2001.922011
