DocumentCode
3086548
Title
Scheduling tests for low power built-in self-test
Author
Schuele, Tobias ; Stroele, Albrecht P.
Author_Institution
Inst. of Comput. Design & Fault Tolerance, Karlsruhe Univ., Germany
Volume
5
fYear
2001
fDate
2001
Firstpage
247
Abstract
During test, circuits are exposed to an increased switching activity which can rise severe hazards to their reliability due to excessive power consumption and heat dissipation. We consider the problem of scheduling tests under peak power constraints such that the total energy consumption is minimized. The proposed method takes into account switching activity which occurs in overlapping regions of the subcircuits under test by means of a hierarchical approach to power estimation
Keywords
automatic testing; built-in self test; circuit reliability; circuit testing; logic testing; low-power electronics; parameter estimation; power consumption; scheduling; built-in self-test; energy consumption; hazards; heat dissipation; hierarchical approach; overlapping; power consumption; power estimation; reliability; scheduling tests; subcircuits; switching; Automatic testing; Built-in self-test; Circuit testing; Energy consumption; Fault tolerance; Hazards; Logic testing; Processor scheduling; Registers; Switching circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location
Sydney, NSW
Print_ISBN
0-7803-6685-9
Type
conf
DOI
10.1109/ISCAS.2001.922031
Filename
922031
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