A 16nm FinFET CMOS technology for mobile SoC and computing applications

Author

Shien-Yang Wu ; Lin, Colin Yu ; Chiang, M.C. ; Liaw, J.J. ; Cheng, J.Y. ; Yang, S.H. ; Liang, Ming ; Miyashita, Tadakazu ; Tsai, C.H. ; Hsu, B.C. ; Chen, H.Y. ; Yamamoto, Takayuki ; Chang, S.Y. ; Chang, V.S. ; Chang, C. Hwa ; Chen, J.H. ; Chen, H.F. ; Tin

Author_Institution

Taiwan Semicond. Manuf. Co., Hsinchu, Taiwan

fYear

2013

fDate

9-11 Dec. 2013

Abstract

For the first time, we present a state-of-the-art energy-efficient 16nm technology integrated with FinFET transistors, 0.07um² high density (HD) SRAM, Cu/low-k interconnect and high density MiM for mobile SoC and computing applications. This technology provides 2X logic density and >35% speed gain or >55% power reduction over our 28nm HK/MG planar technology. To our knowledge, this is the smallest fully functional 128Mb HD FinFET SRAM (with single fin) test-chip demonstrated with low Vccmin for 16nm node. Low leakage (SVt) FinFET transistors achieve excellent short channel control with DIBL of <;30 mV/V and superior Idsat of 520/525 uA/um at 0.75V and Ioff of 30 pA/um for NMOS and PMOS, respectively.

Keywords

CMOS integrated circuits; MOSFET; SRAM chips; copper; integrated circuit interconnections; system-on-chip; Cu; Cu-low-k interconnect; FinFET CMOS technology; FinFET transistors; HD FinFET SRAM; HK-MG planar technology; NMOS; PMOS; computing applications; high density MiM; high density SRAM; logic density; mobile SoC; short channel control; size 16 nm; storage capacity 128 Mbit; FinFETs; High definition video; Logic gates; Metals; Random access memory;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting (IEDM), 2013 IEEE International

Conference_Location

Washington, DC

Type

conf

DOI

10.1109/IEDM.2013.6724591

Filename

6724591