Deriving accurate ASIC cell fault models for VITAL compliant VHDL simulation

Author

Shaw, Don ; Al-Khalili, D. ; Rozon, Côme

Author_Institution

Dept. of Electr. & Comput. Eng., R. Mil. Coll. of Canada, Kingston, Ont., Canada

Volume

5

fYear

2001

fDate

2001

Firstpage

263

Abstract

This paper introduces a system for deriving accurate, technology specific fault models using analog defect simulation. It is implemented by a new software tool that provides a push-button solution for the tedious task of obtaining accurate ASIC cell defect to fault mappings. After completion of the cell defect analysis, the tool generates VITAL compliant, defect-injectable, VHDL cell models. These provide an efficient means to conduct accurate fault simulation of ASIC standard cell designs

Keywords

application specific integrated circuits; automatic testing; fault simulation; hardware description languages; integrated circuit design; integrated circuit testing; ASIC cell defect; ASIC cell fault models; ASIC standard cell designs; CMOS; VHDL simulation; VITAL; analog defect simulation; cell defect analysis; fault mappings; fault simulation; push-button solution; software tool; Application specific integrated circuits; CMOS technology; Circuit faults; Circuit simulation; Computational modeling; Computer simulation; Integrated circuit modeling; Military computing; Semiconductor device modeling; Software tools;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on

Conference_Location

Sydney, NSW

Print_ISBN

0-7803-6685-9

Type

conf

DOI

10.1109/ISCAS.2001.922035

Filename

922035