Deriving accurate ASIC cell fault models for VITAL compliant VHDL simulation

This paper introduces a system for deriving accurate, technology specific fault models using analog defect simulation. It is implemented by a new software tool that provides a push-button solution for the tedious task of obtaining accurate ASIC cell defect to fault mappings. After completion of the cell defect analysis, the tool generates VITAL compliant, defect-injectable, VHDL cell models. These provide an efficient means to conduct accurate fault simulation of ASIC standard cell designs