Title :
Design trade-off in merged DRAM logic for video signal processing
Author :
Chang, Sunho ; Kim, Lee-Sup
Author_Institution :
Korea Adv. Inst. of Sci. & Technol., Taejon, South Korea
Abstract :
The trade-off in designing merged DRAM logic (MDL) is explored for video signal processing. Computing requirements and memory bandwidths are quantitatively analyzed in the programmable MDL architecture. The number of processing elements (NPE) and the number of bus width (NBW) are obtained as a function of macro block rate, clock frequency, data rate, and number of clock/memory access cycles. Optimal MDL design parameters are determined from the minimum cost and design metrics: DRAM access rate (DAR) and area ratio of DRAM (ARD)
Keywords :
application specific integrated circuits; digital signal processing chips; integrated circuit design; random-access storage; video signal processing; DRAM access rate; area ratio; bus width; clock frequency; clock/memory access cycles; data rate; design metrics; macro block rate; memory bandwidths; merged DRAM logic; processing elements; programmable MDL architecture; video signal processing; Bandwidth; Clocks; Computer architecture; Cost function; Frequency; Logic design; Merging; Random access memory; Signal design; Video signal processing;
Conference_Titel :
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location :
Sydney, NSW
Print_ISBN :
0-7803-6685-9
DOI :
10.1109/ISCAS.2001.922036
