Challenges and characterization of 14nm N-type bulk FinFET

FinFET device has better electrostatic performance than planar device and makes devices further scaling possible. N-type bulk FinFET process challenges such as implantation induced Fin damages, Source/Darin (S/D) epitaxy and Fin profile control were discussed. Pre-Fin anti-punch trough (APT) implantation and low beam current n-type light-doped-drain (NLDD) implantation combined with optimized post-implant annealing are both benefit to eliminate or reduce the implantation induced Fin damages. Within S/D Si epitaxy process, contact resistance, resistor resistance and transistor external resistance were much reduced. With the optimized process, n-type bulk FinFET device performance was much improved. Gate oxide performance and electron mobility were compared with previous generations; swing slope and drain induced barrier lowering were also got from the IdVg curves. Some reliability evaluations such as GOI, TDDB and HCI were performed and passed the specifications. For n-type bulk FinFET further improvement directions were proposed at last.