Methodology and Toolset for ASIP Design and Development Targeting Cryptography-Based Applications

Network processors utilizing general-purpose instruction-set architectures (ISA) limit network throughput due to latency incurred from cryptography and hashing applications (AES, DES, MD5, and SHA). This paper presents a methodology using computer-aided design, for development of high-performance application-specific instruction-sets (ASIP) targeting applications saturated in repetitive sequential bitwise operations and data-flow dependencies, thus exposing both fine and coarse grain parallelism through a set of recurring pattern extraction tools. These specific instructions, in conjunction with a minimal set of general-purpose instructions, are then incorporated into a simplistic, single-cycle CPU architecture, for a comparison (in CPU cycles) with common general-purpose instruction latencies (Intel P4). We show that the high-performance instruction set derived, based on the proposed methodology, has the potential for facilitating dramatic improvements in performance (over the software kernel implementation) with substantially increased throughput. Results show that up to 93% of the code is utilized by the instructions derived through the developed toolset resulting with up to 2. 7times cycle time improvement.