Techniques to improve read noise margin and write margin for bit-cell of 14nm FINFET node

The implementation of FINFET devices in the SRAM cell provides many benefits over that of planar bulk devices. The short channel effect, drive current and mismatch can be better controlled. Several FIN number options among PU(pull up device), PD(pull down device) and PG(pass gate device) can be selected to achieve the good read noise margin and write margin. But in highest-density SRAM cell, in order to minimize the bit-cell area, 3 devices are designed as one FIN only for each. The write margin is suffered deeply by this option unfortunately Some techniques are presented in this paper to increase the yield window of FINFET SRAM with limited FIN number. Some of them are based on process or device performance optimization, such as PG Vt implant, FIN thickness, channel orientation modification, DG device and asymmetrical device, others are based on circuit design, including bit-cell and periphery circuit, such as read or write assist circuit, 8T or 10T cell. With these actions, the better yield window can be achieved. The side effects of these actions are evaluated also, such as the area penalty, complex process and the cost more.