DocumentCode :
3087138
Title :
A floating-gate-MOS-based multiple-valued associative memory
Author :
Hanyu, Takahiro ; Higuchi, Tatsuo
Author_Institution :
Dept. of Electron. Eng., Tohoku Univ., Sendai, Japan
fYear :
1991
fDate :
26-29 May 1991
Firstpage :
24
Lastpage :
31
Abstract :
A digit-serial, multiple-valued associative memory VLSI for high-speed information search is presented. Input and output data of a processing element (PE) in the VLSI are directly encoded by appropriate multiple-valued digits, respectively, so that search operations are efficiently described by the combination of a multiple-valued down literals and pass gates. Moreover, multiple-valued memory information is stored in each PE by programming the threshold of the down literal which can be easily implemented using special MOS transistors, called floating-gate MOS transistors. It is demonstrated that the number of interconnections and transistors in the 5-valued associative memory can be reduced to 25% and 53%, respectively, in comparison with the corresponding binary implementation
Keywords :
MOS integrated circuits; VLSI; content-addressable storage; many-valued logics; search problems; 5-valued associative memory; VLSI; floating-gate MOS transistors; floating-gate-MOS-based; high-speed information search; multiple-valued associative memory; multiple-valued digits; multiple-valued down literals; multiple-valued memory information; number of interconnections; pass gates; search operations; threshold; Associative memory; Circuits; Information retrieval; Logic devices; MOS devices; MOSFETs; Nonvolatile memory; Random access memory; Registers; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Multiple-Valued Logic, 1991., Proceedings of the Twenty-First International Symposium on
Conference_Location :
Victoria, BC
Print_ISBN :
0-8186-2145-1
Type :
conf
DOI :
10.1109/ISMVL.1991.130700
Filename :
130700
Link To Document :
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