DocumentCode
3087199
Title
Design of GHz VLSI clock distribution circuit
Author
Zeng, Xuan ; Zhou, D.
Author_Institution
Dept. of Electr. Eng., Fudan Univ., Shanghai, China
Volume
5
fYear
2001
fDate
2001
Firstpage
391
Abstract
In this paper, we derive a formula for running the clock signal in a pipeline fashion to meet the GHz frequency challenge. Moreover we present an optimal algorithm for simultaneous balanced planar tree routing and optimal buffer insertion to reach the GHz limit. To ensure the signal integrity, we have developed a very efficient transmission line based simulator, which plays a key role in verifying the clock circuit performance. The proposed method is successfully used to design a real industrial GHz CPU
Keywords
VLSI; buffer circuits; clocks; integrated circuit layout; logic CAD; microprocessor chips; network routing; pipeline processing; VLSI; clock circuit performance; clock distribution circuit; clock signal; industrial GHz CPU; optimal buffer insertion; pipeline fashion; simultaneous balanced planar tree routing; transmission line based simulator; Circuit optimization; Circuit synthesis; Clocks; Delay; Distributed parameter circuits; Frequency; Routing; Transmission line theory; Very large scale integration; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location
Sydney, NSW
Print_ISBN
0-7803-6685-9
Type
conf
DOI
10.1109/ISCAS.2001.922067
Filename
922067
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