Title :
Steiner tree optimization for buffers. Blockages and bays
Author :
Alpert, Charles J. ; Gandham, Gopal ; Hu, Jiang ; Neves, Jose L. ; Quay, Stephen T. ; Sapatnekar, Sachin S.
Author_Institution :
IBM Austin Res. Lab., Minnesota Univ., MN, USA
Abstract :
Buffer insertion is essential for achieving timing closure. This work studies buffer insertion under two types of constraints: (i) avoiding blockages, and (ii) inserting buffers into pre-determined buffer bay regions. We propose a general Steiner tree routing problem to drive this application and present a maze-routing based heuristic. We show that this approach leads to useful solutions on industry designs
Keywords :
VLSI; buffer circuits; circuit layout CAD; circuit optimisation; integrated circuit layout; network routing; timing; trees (mathematics); Steiner tree optimization; buffer insertion; constraints; industry designs; maze-routing based heuristic; pre-determined buffer bay regions; routing problem; timing closure; Costs; Routing; Tiles; Tree graphs; Wire; Wiring;
Conference_Titel :
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location :
Sydney, NSW
Print_ISBN :
0-7803-6685-9
DOI :
10.1109/ISCAS.2001.922069
