DocumentCode
3087231
Title
Steiner tree optimization for buffers. Blockages and bays
Author
Alpert, Charles J. ; Gandham, Gopal ; Hu, Jiang ; Neves, Jose L. ; Quay, Stephen T. ; Sapatnekar, Sachin S.
Author_Institution
IBM Austin Res. Lab., Minnesota Univ., MN, USA
Volume
5
fYear
2001
fDate
2001
Firstpage
399
Abstract
Buffer insertion is essential for achieving timing closure. This work studies buffer insertion under two types of constraints: (i) avoiding blockages, and (ii) inserting buffers into pre-determined buffer bay regions. We propose a general Steiner tree routing problem to drive this application and present a maze-routing based heuristic. We show that this approach leads to useful solutions on industry designs
Keywords
VLSI; buffer circuits; circuit layout CAD; circuit optimisation; integrated circuit layout; network routing; timing; trees (mathematics); Steiner tree optimization; buffer insertion; constraints; industry designs; maze-routing based heuristic; pre-determined buffer bay regions; routing problem; timing closure; Costs; Routing; Tiles; Tree graphs; Wire; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location
Sydney, NSW
Print_ISBN
0-7803-6685-9
Type
conf
DOI
10.1109/ISCAS.2001.922069
Filename
922069
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