Threshold behavior of the drift region: The missing piece in LDMOS modeling

One of the greatest remaining difficulties in the compact modeling of LDMOS devices is the modeling of the peaks that appear in the capacitance-voltage characteristics when such devices are operated in the on-state. The link between the on-state capacitance peaks and the potential at the internal drain is explored using TCAD simulations and mathematical analysis. The shortcomings of the existing LDMOS compact models are explained using a sub-circuit analysis of the channel and driftregion components of these models. The results of a TCAD-based investigation into how the channel and drift-region parts of an LDMOS behave, interact, and together determine the potential at the internal drain are presented. An improved LDMOS compact-modeling approach is proposed, and the results of a proof-of-concept model are presented and shown to be better than those from existing models, with comparisons made using both simulated and measured device data.