Hierarchical performance optimization for synthesis of linear analog systems

Author

Doboli, Alex ; Vemuri, Raizga

Author_Institution

VLSI Syst. Design Lab., State Univ. of New York, Stony Brook, NY, USA

Volume

5

fYear

2001

fDate

2001

Firstpage

431

Abstract

This paper presents a hierarchical performance optimization method for high level synthesis of analog systems. The goal is to minimize silicon area while meeting design constraints i.e. AC behavior, op amp gains, slew-rate, power etc. The technique is organized as two successive steps: (1) gain distribution for assigning gains to circuits; and (2) actual performance optimization for finding design parameters that minimize area, realize the assigned circuit gains and meet imposed design constraints. Our experiments show that the proposed method successfully synthesizes analog designs such as filters or communication systems in a reasonable length of time

Keywords

analogue circuits; circuit optimisation; high level synthesis; circuit gain; design constraints; design parameters; gain distribution; hierarchical performance optimization; high level synthesis; linear analog system synthesis; silicon area minimisation; Circuit simulation; Circuit synthesis; Design optimization; Filters; Hardware design languages; High level synthesis; Optimization methods; Performance gain; Signal synthesis; Simulated annealing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on

Conference_Location

Sydney, NSW

Print_ISBN

0-7803-6685-9

Type

conf

DOI

10.1109/ISCAS.2001.922077

Filename

922077