DocumentCode :
3087429
Title :
A study of failures identified during board level environmental stress testing
Author :
Parker, T. Paul ; Webb, Cathy W.
Author_Institution :
AT&T Little Rock Works, Little Rock, AR, USA
fYear :
1992
fDate :
18-20 May 1992
Firstpage :
177
Lastpage :
184
Abstract :
AT&T has investigated and implemented environmental stress testing (EST) in the production of a variety of circuit board designs as a means of reducing the incidence of early life failures. EST techniques include thermal cycling, random vibration, and others. These techniques have proven more effective than traditional burn-in techniques. In addition, studies have revealed that functional monitoring during thermal stressing of circuit cards more than doubles the effectiveness of EST. Outgoing quality audits and customer first month failure rates have improved by factors of two to four since the implementation of EST
Keywords :
environmental testing; failure analysis; life testing; printed circuit testing; production testing; EST techniques; board level environmental stress testing; circuit board designs; early life failures; first month failure rates; functional monitoring; random vibration; thermal cycling; Application software; Assembly; Circuit testing; Failure analysis; Life testing; Manufacturing processes; Printed circuits; Production; Thermal stresses; Total quality management;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Components and Technology Conference, 1992. Proceedings., 42nd
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0167-6
Type :
conf
DOI :
10.1109/ECTC.1992.204204
Filename :
204204
Link To Document :
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