DocumentCode
3087509
Title
Modeling of dynamic errors in algorithmic A/D converters
Author
Folkesson, K. ; Svensson, C. ; Eklund, J.-E.
Author_Institution
Dept. of Phys. & Meas., Linkoping Univ., Sweden
Volume
5
fYear
2001
fDate
2001
Firstpage
455
Abstract
In communication applications, the requirements on A/D converters are high and increasing. To be able to design high-perfomance converters, it is important to understand the speed limitations. In this work, performance decrease caused by dynamic errors related to settling time of the switched circuits at high sampling frequencies is investigated
Keywords
analogue-digital conversion; errors; algorithmic A/D converters; algorithmic ADC; dynamic errors modelling; high sampling frequencies; high-perfomance converters; settling time; speed limitations; switched circuits; Capacitors; Clocks; Frequency; Heuristic algorithms; Sampling methods; Signal resolution; Signal sampling; Switched circuits; Switches; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location
Sydney, NSW
Print_ISBN
0-7803-6685-9
Type
conf
DOI
10.1109/ISCAS.2001.922083
Filename
922083
Link To Document