Title :
A pattern compaction technique for power estimation based on power sensitivity information
Author :
Hsu, ChihYuiig ; Chaur-Wen Wei ; Shen, WenZen
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
We propose an efficient power estimation technique for CMOS combinational circuits based on power sensitivity information of primary inputs. We compacted a large sequence of input patterns into a much smaller ones, which also preserved the statistical properties of the original sequence. The experimental results showed our compaction method achieved high compaction ratio within reasonable loss in the accuracy for average power estimation
Keywords :
CMOS logic circuits; circuit simulation; combinational circuits; graph theory; logic simulation; low-power electronics; CMOS combinational circuits; average power estimation; compaction method; input patterns; loss; pattern compaction technique; power sensitivity information; primary inputs; statistical properties; CMOS technology; Circuit simulation; Combinational circuits; Compaction; Computational modeling; Energy consumption; Hamming distance; Power engineering and energy; Power system simulation; Sampling methods;
Conference_Titel :
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location :
Sydney, NSW
Print_ISBN :
0-7803-6685-9
DOI :
10.1109/ISCAS.2001.922086
