DLL-based multi-FPGA systems clock synchronization

This paper analyzes the feather of clock synchronization in FPGA, which shows, through the rational use for internal particular clock resources: the DLL and clock tree, FPGA´s internal clock skew is reduced to negligible level, which not only realizes on-chip clock synchronization, but also achieves the real clock synchronization when communicating with external devices. This paper also gives a multi-FPGA systems clock synchronization program, in which the input clock is entered into a certain FPGA and the internal DLL is used to generate multi-output clock signals synchronized with the input clock, through reasonable circuit wiring, these signals, respectively, as the clock signal inputting every piece of FPGA, which finally realizes the system clock synchronization.