Title :
An optimization-based low-power voltage scaling technique using multiple supply voltages
Author :
Yeh, Yi-Jong ; Kuo, Sy-Yen
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
In this paper, we proposed a voltage scaling technique with multiple supply voltages for low-power designs. We considered the path sensitization as well as releasing the clustering constraint applied in the CVS (Clustered Voltage Scaling) technique. Our technique operates the gates with the lowest feasible supply voltages and then uses an existing path selection algorithm for optimization. Experiments are conducted on the ISCAS85 benchmarks and the results show that about 20% power on average can be further reduced by our technique in comparison with the CVS technique
Keywords :
CMOS digital integrated circuits; VLSI; circuit CAD; circuit optimisation; integrated circuit design; logic CAD; low-power electronics; clustering constraint; low-power designs; low-power voltage scaling technique; multiple supply voltages; optimization-based voltage scaling technique; path selection algorithm; path sensitization; CMOS digital integrated circuits; Clustering algorithms; Delay; Digital circuits; Dynamic voltage scaling; Energy consumption; Integrated circuit interconnections; Timing; Very large scale integration; Wire;
Conference_Titel :
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location :
Sydney, NSW
Print_ISBN :
0-7803-6685-9
DOI :
10.1109/ISCAS.2001.922103
