DocumentCode
3087941
Title
The 3D stack in short form [memory chip packaging]
Author
Minahan, J.A. ; Pepe, A. ; Some, R. ; Suer, M.
Author_Institution
Irvine Sensors Corp., Costa Mesa, CA, USA
fYear
1992
fDate
18-20 May 1992
Firstpage
340
Lastpage
344
Abstract
A novel form of 3D high-density stack, called a short stack, has been built and tested. One version of the short stack allowed accurate measurement of the T-connect resistance, ≈0.025 ohms, while a second version was designed to provide four memory chips stacked for use in a low headroom application that incorporated the 3D technology with the high-density interconnect multichip approach
Keywords
integrated circuit technology; integrated memory circuits; packaging; 3D high-density stack; T-connect resistance; low headroom application; short stack; stacked memory chips; Assembly; Circuit testing; Lead; Packaging; Random access memory; Semiconductor device measurement; Sputtering; Stacking; Substrates; Temperature;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Components and Technology Conference, 1992. Proceedings., 42nd
Conference_Location
San Diego, CA
Print_ISBN
0-7803-0167-6
Type
conf
DOI
10.1109/ECTC.1992.204230
Filename
204230
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