Title :
Impact of multi-gate device architectures on digital and analog circuits and its implications on System-On-Chip technologies
Author :
Thean, A. ; Wambacq, Piet ; Lee, Jae W. ; Cho, Moon Ju ; Veloso, A. ; Sasaki, Yutaka ; Chiarella, T. ; Miyaguchi, Kenichi ; Parvais, B. ; Bardon, M.G. ; Schuddinck, P. ; Kim, Myung Su ; Horiguchi, Naoto ; Dehan, M. ; Mercha, Abdelkarim ; Van der Plas, G.
Author_Institution :
IMEC, Leuven, Belgium
Abstract :
This paper reviews some important process aspects of aggressively downscaled FinFET technologies and their implications on digital and analog figures of merits (FOMs). The need to downscale device architectures to enhance digital transistor electrostatics and circuit density led to influences in parasitics, variability, and noise, which impact analog FOMs. Therefore, it is important to understand the trade-offs due to the new devices and the upcoming process solutions to address them. Process features, variability and parasitics relevant to 14nm and beyond FinFET will be reviewed and their System-On-Chip (SOC) implications will be discussed.
Keywords :
MOSFET; electrostatics; mixed analogue-digital integrated circuits; system-on-chip; FOM; FinFET; SOC; analog circuits; analog figure of merit; circuit density; digital circuits; digital transistor electrostatics; multigate device architectures; size 14 nm; system-on-chip technology; Epitaxial growth; FinFETs; Layout; Logic gates; Noise; Performance evaluation;
Conference_Titel :
Electron Devices Meeting (IEDM), 2013 IEEE International
Conference_Location :
Washington, DC
DOI :
10.1109/IEDM.2013.6724647