High-performance floating-point implementation using FPGAS

Traditionally, digital signal processing (DSP) is performed using fixed-point or integer arithmetic. The algorithm is carefully mapped into a limited dynamic range, and scaled through each function in the datapath. This requires numerous rounding and saturation steps, and can adversely affect the algorithm performance. Use of floating-point arithmetic provides a large dynamic range and greatly simplifies the task of system performance verification, usually against a floating-point simulation. The drawback is an order of magnitude larger computational requirement, whether using a digital signal processor or FPGA-based simplification. Recently available FPGA design tools and IP provide a substantial reduction in computational resources, as well as greatly easing the implementation effort in a floating-point datapath. Moreover, unlike digital signal processors, an FPGA can support a DSP datapath with mixed floating- and fixed-point operations, and achieve performance in excess of 100 GFLOPS. This is an important advantage, for many high-performance radar, electronic warfare, and sensor fusion applications only require the dynamic-range floating-point arithmetic in a subset of the total signal processing. The choice of FPGA implementation coupled with floating-point tools and IP allows the designer flexibility in a mix of fixed-point data width, floating-point data precision, and performance levels unattainable by a processor-based architecture.