Gate-last integration on planar FDSOI MOSFET: Impact of mechanical boosters and channel orientations

We present for the first time Gate-Last (GL) planar Fully Depleted (FD) SOI MOSFETs featuring both ultra thin silicon body (3-5 nm) and BOX (25 nm). Transistors with metal-last on high-k first (TiN/HfSiON) have been successfully fabricated down to 15nm gate length. We have thoroughly characterized the gate stack (reliability, work-function tuning on Equivalent Oxide Thickness EOT=0.85nm) and transport (hole mobility, R_access) for different surface and channel orientations. We report excellent I_{ON, p}=1020μA/μm at I_{OFF, p}=100nA/μm at V_DD=0.9V supply voltage for <;110> pMOS channel on (001) surface with in-situ boron doped SiGe Raised Source and Drain (RSD) and compressive CESL. This is explained by the high efficiency of the strain transfer into the ultra-thin channel, as evidenced by physical strain measurements (dark field holography).