Research on Configuration Optimization Techniques for Reconfigurable DSP Processor

Author

Duan, Ran ; Wang, Yanning ; Liang, Jie

Author_Institution

Beijing Aerosp. Autom. Control Inst., Beijing, China

fYear

2010

fDate

17-19 Sept. 2010

Firstpage

928

Lastpage

931

Abstract

The paper discusses the configuration optimization scheme of a reconfigurable DSP processor. According to the facts that the coarse-grained reconfigurable computing structures have less configuration information and fast configuration process, a hybrid storage arrangement of data and configuration is proposed. Taking advantages of bus-multiplexing and hybrid storage, the higher memory utilization rate and less on-chip wiring overheads have been achieved.

Keywords

digital signal processing chips; field buses; multiplexing; reconfigurable architectures; bus-multiplexing; coarse-grained reconfigurable computing structures; configuration information; configuration optimization; configuration process; hybrid storage; hybrid storage arrangement; memory utilization rate; on-chip wiring overheads; reconfigurable DSP processor; Arrays; Context; Digital signal processing; Multiplexing; Organizations; System-on-a-chip; Wiring; DSP; bus multiplexing; configuration optimization; reconfigurable computing;

fLanguage

English

Publisher

ieee

Conference_Titel

Pervasive Computing Signal Processing and Applications (PCSPA), 2010 First International Conference on

Conference_Location

Harbin

Print_ISBN

978-1-4244-8043-2

Electronic_ISBN

978-0-7695-4180-8

Type

conf

DOI

10.1109/PCSPA.2010.229

Filename

5635917