Title :
A low-power bit-serial multiplier for finite fields GF(2m)
Author_Institution :
Inst. for Appl. Inf. Processing & Commun., Graz Univ. of Technol.
Abstract :
This paper presents a bit-serial architecture for efficient addition and multiplication in binary finite fields GF(2m) using a polynomial basis representation. Moreover, a low-voltage/low-power implementation of the arithmetic circuits and the registers is proposed. The introduced multiplier operates over a variety of binary fields up to an order of 2m. We detail that the bit-serial multiplier architecture can be implemented with only 28m gate equivalents, and that it is scalable, highly regular and simple to design
Keywords :
Galois fields; digital arithmetic; low-power electronics; multiplying circuits; GF(2m); addition; arithmetic circuit; binary finite field; bit-serial multiplier; low-voltage low-power architecture; multiplication; polynomial basis; register cell; Additives; Arithmetic; Codes; Elliptic curve cryptography; Elliptic curves; Galois fields; Hardware; Polynomials; Smart cards; Very large scale integration;
Conference_Titel :
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location :
Sydney, NSW
Print_ISBN :
0-7803-6685-9
DOI :
10.1109/ISCAS.2001.922163
