A 200 MHz 1.2 W 1.4 GFLOPS microprocessor with graphic operation unit

This 200 MHz CMOS 2-issue superscalar microprocessor is redesigned with a 0.25 /spl mu/m 5-metal-layers CMOS process (L/sub eff/=0.20 /spl mu/m). In this chip 3.2M transistors are implemented in a 7.6/spl times/7.6 mm/sup 2/ die. This chip for low-cost graphic, embedded applications achieves 1.4 GFLOPS at 200 MHz with low-power consumption. This chip integrates CPU, FPU, 8 kB direct-mapped instruction cache (IC), 16 kB direct-mapped data cache (DC), MMU (64-entry unified TLB and 4-entry ITLB), bus interface logic, and six peripherals which are DMAC, timer unit (TMU), real time clock (RTC), serial comm. interface (SCI), interrupt controller (INTC), and emulation/debug unit (EMU). The bus interface provides glueless connections to SRAM, DRAM, SDRAM, burst-ROM, and PCMCIA, bus operation includes 8-, 16-, 32-, and 64b bus widths.