A group IV solution for 7 nm FinFET CMOS: Stress engineering using Si, Ge and Sn

Band gap and stress engineering using group IV materials - Si, Ge and Sn and their alloys is employed to design a FinFET-based CMOS solution for the 7 nm technology node and beyond. A detailed simulation study evaluating the performance of the proposed design is presented. Through the use of a common strain-relaxed buffer layer for p, n channel MOSFETs and a careful selection of source/drain stressor materials, the CMOS design is shown to achieve performance benefits over strained-Si, meet the I_OFF requirements and provide a path for continued technology scaling. Some of the critical challenges in realizing the proposed CMOS design are also investigated through experimental methods.