Title :
Packaging technology for the NEC ACOS System 3900
Author :
Yamada, Masahiro ; Nishiyama, Michiaki ; Tokaichi, Tetsuro ; Okano, Minoru
Author_Institution :
NEC Corp., Tokyo, Japan
Abstract :
The packaging technologies adopted in the NEC ACOS System 3900 are described. A new high-density surface-mount technology was adopted to further reduce the distance between the LSI chips, based on the high-speed LSI technology and the LSI multichip packaging technology used in the supercomputer SX-3. The system uses as a processor a multichip package (MCP) which can mount up to 100 VLSIs with a maximum of 20000 gates per VLSI and 70-ps delay time per gate. To connect MCPs over the shortest distance, MCPs are mounted on both sides of single 42-layer printed wiring board (PWB). A new surface-mount zero insertion force (ZIF) connector has been developed to implement this double mounting of MCPs. This ZIF connector is a high-density surface-mount connector having 9440 contacts on one side of the pad arranged in a 2.54-mm staggered grid on the PWB surface. This makes it possible to connect the MCP and the PWB at once with high reliability. The main memory unit is described
Keywords :
NEC computers; VLSI; general purpose computers; microcomputers; multichip modules; packaging; surface mount technology; tape automated bonding; LSI multichip packaging; NEC ACOS System 3900; PWB surface; TAB; high-density surface-mount connector; high-density surface-mount technology; high-speed LSI technology; main memory unit; packaging technologies; single-board processor; three-level hierarchy; zero insertion force connector; Connectors; Contacts; Delay effects; Large scale integration; National electric code; Packaging; Supercomputers; Surface-mount technology; Very large scale integration; Wiring;
Conference_Titel :
Electronic Components and Technology Conference, 1992. Proceedings., 42nd
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0167-6
DOI :
10.1109/ECTC.1992.204288
